This invention relates in general to a tape-automated-bonding (TAB) bonded semiconductor device, and more particularly to a TAB bonded semiconductor device having off-chip power and ground distribution.
Today's VLSI devices integrate a large number of functions in a single integrated circuit chip. As the integration level has increased, the circuit network and the required signal transmission rate through that network have increased as well. In order to achieve a high signal transmission rate, circuit designers have attempted to avoid the use of long power and ground busses within the chip and have instead provided output drivers and receivers in close proximity to external contact sites or bonding pads on the surface of the chip. Using this design method often requires that package interconnection circuitry and input-output (I/O) pins be provided for power and ground connection at many different locations around the chip. The introduction of extra I/O pins increases the amount of space necessary to mount the packaged device on a mounting substrate such as a printed-circuit-board (PCB). One solution is to interconnect the contact pads within the chip itself; however, the interconnection of output drivers and receivers through power and ground busses within the device consumes valuable space and results in high inductance transmission lines.
Another potential solution is to use a conventional leadframe for off-chip signal transmission and wire bond one or more bonding pads to a single outer lead in the leadframe. Several wire bonded designs have been developed, see for example, U.S. Pat. No. 4,937,656 to M. Kohara. However, conventional wire bonding cannot meet the bonding pad pitch spacing requirements of many VLSI devices. A preferred method for bonding tightly spaced bonding pads on a VLSI device to external package circuitry is TAB bonding.
Various TAB tape designs have been developed to address the inner lead bonding requirements of different package types. Shown in FIG. 1, in plane view, is a section of a copper leaded two-layer TAB tape 10 formed in accordance with the prior art. TAB Tape 10 includes a punched polymer tape 12 supporting a patterned copper metal layer having a thickness of about 20 to 40 microns. The copper metal layer is laminated to polymer tape 12 and photolithographically patterned and etched to form a series of individual copper leads 14. Sections of polymer tape 12 are punched out to permit the proximal ends of leads 14 to be bonded to a semiconductor device (not shown) and to permit the distal ends to be forged into a shape suitable for connection to outer leads, such as those provided by a conventional leadframe, or bonded directly to a substrate such as a PCB. The TAB tape shown in FIG. 1 is configured for inner lead bonding to a semiconductor device having peripheral bonding pads arrayed on all sides of the face surface of the device. Upon bonding and encasement in an insulating package body, a packaged device such as a quad-flat-package (QFP) is formed. Other four sided and two sided inner lead bonding configurations provided in a TAB format are well known in the art and include, for example, dual-in-line (DIP) and small-outline-J-lead (SOJ) type packages.
Selected ones of leads 14 are designated to provide external signal paths for ground and power distribution networks within the semiconductor device. A TAB bonded semiconductor device using the TAB tape shown in FIG. 1, must have circuit networks within the semiconductor device itself in order to facilitate the delivery of ground and power signals across the semiconductor device to selected external leads 14. Thus there remains a need for a packaged semiconductor device in a TAB format having low inductance off-chip power and ground distribution bussing.